1. Field of the Invention
The present invention relates to a semiconductor memory device having a memory cell area and a peripheral circuit area, and relates, more particularly, to a semiconductor memory device in which a difference in level between the memory cell area and the peripheral circuit area is reduced.
2. Description of the Related Art
There has recently been an increasingly diversified demand for a larger capacity, a higher processing speed, etc. of a very large-scale integrated circuit (VLSI) from the market. Particularly, this trend is acutely observed in a semiconductor memory device called a dynamic random access memory (DRAM) having memory cells.
While the number of memory cells in one semiconductor memory device is increasing along with an increase in capacity in one hand, an increase in the area of an integrated circuit has also been restricted on the other hand with a reduced size of unit area per one memory cell based on the development of fining technologies at various manufacturing stages.
When the unit area per one memory cell is reduced, in order to amplify a signal for showing a state (cell xe2x80x9cHIGHxe2x80x9d) that a charge has been stored in a memory cell as the cell xe2x80x9cHIGHxe2x80x9d without a malfunction, it becomes necessary to secure a charge level (cell capacity) to be stored in each memory cell at a predetermined level or above.
For this purpose, a stacked-type memory cell is used, for example. In a stacked-type memory cell, an electrode for storing a charge for constituting a capacitor in which a charge is stored is formed at a position higher than a semiconductor substrate. This capacitor is structured by the electrode for storing a charge, a thin separating insulating film formed on the electrode, and a cell plate formed on the insulating film.
Accordingly, in a semiconductor device formed with an electrode for storing a charge, there exists a large difference in level between a peripheral circuit area, other than a memory cell area, in which the electrode for storing a charge is not formed and an area in which memory cells are formed. In other words, a large difference in height exists.
A signal wiring layer for selecting a sense amplifier circuit connected to a bit line is positioned, for example, as a higher layer than a layer in which a capacitor is formed and is formed by an aluminum wiring layer made of aluminum or the like. This sense amplifier circuit is formed in a peripheral circuit area of a semiconductor memory device. Accordingly, the signal wiring layer is formed in a boundary area formed with a sharp difference in level from the peripheral circuit area to the memory cell area.
Accordingly, the following problems occur in a process of forming a metal wiring layer such as an aluminum wiring layer that is a layer after the process of forming the capacitor.
In the process of forming a wiring layer, after a conductive film that is to be the wiring layer is formed, a wiring layer-shaped photoresist pattern is formed on this film by a photolithography technique. However, if there is a sharp difference in level as described above, there arises a large difference in focal points between the memory cell area and the peripheral circuit area at the time of exposing a photoresist to a light for forming the photoresist pattern. Therefore, a margin of a depth of focus for a light exposure is narrowed substantially.
As a result, in the worst case, there occurs the following situation after an exposure and development that the photoresist disappears from within an area that should remain as an area in which an aluminum wiring layer is to be formed. On the other hand, it occurs the photoresist remains in an area that should be removed by the development as an area in which the aluminum wiring layer is not to be formed. If the conductive film is etched in this state in an attempt to form a wiring layer, disconnection and short-circuiting of the wiring may occur. Such an inconvenience in the process of forming a wiring layer or the like finally results in a manufacturing of a fatal defective product as a semiconductor memory device.
To avoid the above problem, there has been provided a semiconductor memory device in which dummy memory cells that are not charged with or do not discharge any electric charge are disposed in a ring shape around an outermost peripheral portion of the memory cell area. These dummy memory cells are disposed adjacent to real memory cells to which electric charges are charged and which discharge the electric charges as actual memory cells in the memory cell area.
When the dummy memory cells are disposed in this way, the sharp difference in level between the memory cell area and the peripheral circuit area other than the memory cell area is suppressed. Accordingly, this restricts an occurrence of a defective photoresist pattern attributable to this level difference in the process of exposing and developing the photoresist and an occurrence of defective products due to the pattern failure.
There is disclosed a method for reducing a level difference by forming a dummy layer in Japanese Patent Application Laid-open Publication No. Hei 4-82263. FIG. 1 is a cross-sectional view for showing a semiconductor memory device described in Japanese Patent Application Laid-open Publication No. Hei 4-82263.
According to the semiconductor memory device described in Japanese Patent Application Laid-open Publication No. Hei 4-82263, a dummy layer 314 formed on an inter-layer insulating film 313 is provided on only a peripheral circuit area 312 other than a memory cell area 311. Then, a silicon oxide film 316 is formed on the whole top surfaces to make a flat surface. Further, a metal wiring layer 317 such as an aluminum wiring layer or the like is formed on the silicon oxide film 316.
Further, in Japanese Patent Application Laid-open Publication No. Hei 4-87366, there is disclosed a method for reducing a level difference by providing an element separating area having shielding electrodes and dummy level-difference parts in a boundary area between a memory cell area and a peripheral circuit area. FIG. 2 is a cross-sectional view for showing a semiconductor memory device described in Japanese Patent Application Laid-open Publication No. Hei 4-87366.
According to the semiconductor memory device described in Japanese Patent Application Laid-open Publication No. Hei 4-87366, there is provided an element separating area 403 between a memory cell area 401 and a peripheral circuit area 402. This element separating area 403 is provided with shielding electrodes 406a and 406b, and dummy level-difference parts 410a and 410b formed on the shielding electrodes 406a and 406b respectively.
These conventional semiconductor memory devices, however, have the following problems.
According to the conventional semiconductor memory device provided with dummy memory cells, there is a risk of an increase in the area of the integrated circuit as the dummy memory cells are formed in a ring shape around the outermost peripheral portion of the memory cell area. The area formed with the dummy memory cells is entirely a redundant area.
Further, the sharp difference in level between the dummy memory cells and the peripheral circuit area has not almost been reduced. Accordingly, it is not possible to completely prevent an occurrence of a defective photoresist pattern attributable to this sharp level difference between the memory cell area and the peripheral circuit area in the process of exposing and developing the photoresist and an occurrence of defective products due to the pattern failure.
According to the conventional semiconductor memory device described in Japanese Patent Application Laid-open Publication No. Hei 4-82263, it is necessary to form the dummy layer 314 on the peripheral circuit area 312 other than the memory cell area 311 before the process of forming the metal wiring layer 317 such as an aluminum wiring layer or the like. Therefore, it is necessary to add this new process. This results in an increase in the number of processes.
According to the conventional semiconductor memory device described in Japanese Patent Application Laid-open Publication No. Hei 4-87366, the element separating area 403 having the shielding electrodes 406a and 406b and the dummy level-difference parts 410a and 410b is formed between the memory cell area 401 and the peripheral circuit area 402. Therefore, this increases the area of the integrated circuit. Further, similar to the semiconductor memory device provided with the dummy memory cells, the element separating area 403 having the shielding electrodes 406a and 406b and the dummy level-difference parts 410a and 410b is an entirely redundant area.
It is an object of the present invention to provide a semiconductor memory device having a memory cell area and a peripheral circuit area that can be manufactured without an additional new manufacturing process, that enables the device to be further highly integrated and that can reduce an occurrence of line disconnection and short-circuiting and the like.
A semiconductor memory device having a memory cell area and a peripheral circuit area according to the present invention, comprises a semiconductor substrate divided into a memory cell area provided with a plurality of memory cells, a peripheral circuit area provided with a plurality of circuits for controlling the operation of the memory cells, which peripheral circuit area is provided around the memory cell area, and a boundary area provided between the memory cell area and the peripheral circuit area. A first wiring layer is formed in the memory cell area on the semiconductor substrate. A first inter-layer insulating film for covering the first wiring layer is formed on the semiconductor substrate. A second wiring layer is formed in the memory cell area on the first inter-layer insulating film. A second inter-layer insulating film for covering the second wiring layer is formed on the first inter-layer insulating film. A signal wiring connected to at least one of the circuits is formed in the boundary area on the second inter-layer insulating film. A dummy wiring is formed of the same layer as the first wiring layer or the second wiring layer below the signal wiring.
Another semiconductor memory device having a memory cell area and a peripheral circuit area according to the present invention, comprises a semiconductor substrate divided into a memory cell area provided with a plurality of memory cells, a peripheral circuit area provided with a plurality of circuits for controlling the operation of the memory cells, which peripheral circuit area is provided around the memory cell area, and a boundary area provided between the memory cell area and the peripheral circuit area. A first wiring layer is formed in the memory cell area on the semiconductor substrate. A first inter-layer insulating film for covering the first wiring layer is formed on the semiconductor substrate. A second wiring layer is formed in the memory cell area on the first inter-layer insulating film. A second inter-layer insulating film for covering the second wiring layer is formed on the first inter-layer insulating film. A conductive layer is formed in the memory cell area on the second inter-layer insulating film. A third inter-layer insulating film for covering the conductive layer is formed on the second inter-layer insulating film. A signal wiring connected to at least one of the circuits is formed in a boundary area on the third inter-layer insulating film. A dummy wiring is formed of the same layer as the conductive layer below the signal wiring.
According to the present invention, there is formed the dummy wiring in the boundary area of the same layer as a wiring layer or the conductive layer in a memory cell area which is formed in a layer lower than a signal wiring layer in the boundary area. Therefore, it is possible to reduce a level difference between the memory cell area and a peripheral circuit area. Accordingly, it is possible to reduce an occurrence of disconnection and short-circuiting of the wiring and the like in the boundary area. Further, as no redundant area is formed, it is possible to achieve a higher integration of the semiconductor memory device. Furthermore, the device can be manufactured without requiring an additional manufacturing process.